I. Field of the Disclosure
The technology of the disclosure relates generally to fabrication of complementary metal oxide semiconductor (CMOS) devices, and more specifically, to forming source/drain structures in CMOS devices.
II. Background
Transistors are essential components in modern electronic devices, and large numbers of transistors are employed in integrated circuits (ICs) therein. For example, components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors for logic circuits and memory devices.
As electronic devices become more complex in functionality, so does the need to include a greater number of transistors in such devices. But as electronic devices are provided in increasingly smaller packages, such as in mobile devices for example, there is a need to provide a greater number of transistors in a smaller IC chip. This increase in the number of transistors is achieved in part through continued efforts to miniaturize transistors in ICs (i.e., placing increasingly more transistors into the same amount of space). As a result, gate lengths are also scalably reduced, thereby reducing channel length of the transistors and interconnects. This reduction in gate length has created a need to move from planar transistors into gate all around (GAA) transistors. In particular, as channel length in planar transistors is reduced such that the channel length is of the same order of magnitude as depletion layer widths, short channel effects (SCEs) can occur that degrade performance. More specifically, SCEs in planar transistors cause increased current leakage, reduced threshold voltage, and/or threshold voltage roll-off (i.e., reduced threshold voltage at shorter gate lengths), and therefore, reduced gate control.
In this regard, GAA transistors have been developed. In GAA transistors, gate material wraps around at least a portion of a channel structure to provide better gate control over an active channel therein. Better gate control provides reduced current leakage and increased threshold voltage compared to a planar transistor of a similar footprint. An example is a complementary metal oxide semiconductor (CMOS) fin field effect transistor (FET) (FinFET). A FinFET provides a channel structure formed by thin silicon (Si) “fins,” and a gate that wraps around portions of the fins. FIG. 1 illustrates a conventional CMOS FinFET 100 (“FinFET 100”) as an example. The FinFET 100 includes a substrate 102 and fins 104A and 104B disposed above the substrate 102 to form a semiconductor material structure 106 across the FinFET 100. The fins 104A and 104B are made of a semiconductor material, such as Silicon (Si) for example. The FinFET 100 further includes source/drain elements 108A, 108B disposed above the fins 104A and 104B, respectively, to provide a source/drain to the FinFET 100. It is noted that similar source/drain elements are disposed on a side 110 of the FinFET 100, but are not shown in FIG. 1 for the sake of clarity. The FinFET 100 further includes a source/drain contact 112 disposed on the substrate 102 to provide a contact to the source/drain elements 108A, 108B. The FinFET 100 further includes a source/drain contact 114 to provide a contact to the source/drain regions (not shown) disposed on the side 110 of the FinFET 100. The FinFET 100 further includes spacer layers 116A and 116B disposed on the substrate 102 to isolate the source/drain contacts 112, 114, respectively, from a “wrap-around” gate 118 disposed over the fins 104A and 104B. The spacer layers 116A and 116B may be a Nitride-based low-k gate spacer or an air spacer. The FinFET 100 further includes the gate 118 disposed on the substrate 102 and above the fins 104A and 104B between the spacer layers 116A and 116B. The FinFET 100 further includes a gate contact 120 disposed on the gate 118 to provide a contact to the gate 118. The FinFET 100 further includes an interlayer dielectric (ILD) 122 to isolate active components of the FinFET 100 from other devices disposed near the FinFET 100. It is noted that, as used herein, the term “source/drain element” denotes that the “element” can be either a source or a drain of a corresponding CMOS device based on how the CMOS device is connected in the circuit, since the conduction channel has no intrinsic polarity.
With continuing reference to FIG. 1, the source/drain elements therein, such as source/drain element 108A, are grown on the fin 104A using an epitaxial process. Conventionally, epitaxially grown source/drain elements, such as source/drain elements 108A and 202A illustrated in FIG. 2, have been used to provide low contact resistance and channel strain. Contact resistance is a limiting factor in fabrication of CMOS devices, with high contact resistance resulting in degradation of performance, errors in data, and increase heat and power loss, to name a few effects. It is desirable then to achieve low contact resistance. A low contact resistance is obtained in a CMOS device, such as FinFET 100, by having as large as possible a contact area between a source/drain region, such as source/drain region 108A, and a channel structure therein, such as fin 104A.
In this regard, FIG. 2 illustrates in further detail the source/drain element 108A of the FinFET 100 illustrated in FIG. 1. As illustrated in FIG. 2, the channel structure of the FinFET 100, i.e., the fin 104A, is very thin. Thus, merely disposing a source/drain region (not shown) above the fin 104A in contact with a top portion 202 of the fin 104A will provide a relatively large contact resistance. Accordingly, in the FinFET 100, epitaxial growth is employed above and around the fin 104A to provide oversized source/drain elements 108A, 204A that cover the top portion 202 and side portions 206, 208 of the fin 104A.
The use of controlled mechanical strain is widely used to boost mobility. In FIG. 2, the source/drain element 108A, in conjunction with the counterpart source/drain region 204A, provide a channel strain to the FinFET 100. In particular, source/drain element 108A and 204A can be configured to provide compressive stress when the FinFET 100 is a p-type MOS (pMOS) FinFET, and tensile stress when the FinFET 100 is an n-type MOS (nMOS) FinFET. Providing the appropriate channel strain improves mobility and speed of the FinFET 100. For example, the source/drain elements 108A, 204A can include Silicon Germanium (SiGe) because Germanium (Ge) has an atom larger than Silicon (Si), and therefore, will push the Silicon (Si) channel structure towards the center of the FinFET 100, thus providing compressive stress to the channel Accordingly, epitaxially growing the source/drain elements 108A and 204A on the fin 104A provides low contact resistance and desirable channel strain, thus improving performance of the FinFET 100.
Further scaling down of CMOS devices, however, has reduced the effective epitaxial growth of source/drain regions. For example, with reference back to FIG. 1, scaling down of a CMOS device, such as FinFET 100 illustrated in FIG. 1, can include reducing a fin pitch 124. Reducing the fin pitch 124, for example to 24 nanometers (nm) or below, may cause the source/drain element 108A to contact and short a source/drain region of an adjacent CMOS device (not shown). Although such effect may be countered by reducing the size of the adjacent source/drain regions to maintain a separation therein, reducing the size of the source/drain region also reduces the contact area between the source/drain region and a corresponding channel structure. This increases contact resistance, which may result in loss of performance, errors in data, and increased heat and power loss, to name a few effects. Scaling down of a CMOS device may further include reducing a fin width 126. However, reducing the fin width 126 also reduces the contact area between the source/drain region and a corresponding channel structure which, as noted earlier, increases contact resistance and may result in loss of performance, errors in data, and increased heat and power loss. Furthermore, growing the epitaxial source/drain element in a narrower fin 104A, 104B makes it difficult to confine the volume of the source/drain element to the body of the fin 104A, 104B, for example Silicon (Si). This, in turn, makes it difficult for the source/drain region to have the necessary mechanical support in the fin 104A, 104B to provide an adequate channel strain to the channel structure therein, resulting in a weaker channel strain, and thus reducing mobility and speed of the transistor.